(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory (DRAM) having an increased capacitance capacitor using a self-aligned method to increase capacitor area.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In their U.S. Pat. No. 5,140,389 to Kimura et al, the inventors describe various embodiments of stacked capacitors. U.S. Pat. Nos. 5,059,548 to Kim and 5,146,300 to Hamamoto et al show stacked capacitor processes and resulting structures. U.S. Pat. No. 5,047,817 to Wakamiya et al describes etching the lower electrode area of the capacitor into various concave/convex shapes in order to increase the surface area and capacitance of the capacitor.
A typical stacked capacitor of the prior art is illustrated in FIG. 1. Device structures are shown in and on a semiconductor substrate 10. Field oxide regions 11 isolate device regions. Gate electrodes 14 are shown overlying gate oxide layer 12. The bottom node of the capacitor 32 is shown contacting the capacitor node contact region 28. Completing the capacitor are the dielectric layer 34 and top electrode layer 36. A thick insulating layer 38 covers the capacitor and device structures. A conducting layer 40 completes connection to the bit line contact region 29.